Electrically erasable read only memory cell array having elongated control gate in a trench

U.S. Patent Number: 5258634

Abstract: An EPROM cell on a semiconductor substrate having a trench containing a source region in the bottom thereof, insulated floating gates on opposite sidewalls of the trench, and a control gate overlying the floating gates. Drain regions are provided beneath the top surface of the substrate, adjacent to the floating gates, which are electrically connected by a conductive stripe on the surface of the substrate that extends transverse to the trench axis. A method of fabricating an EPROM cell by forming a trench in a semiconductor substrate. An insulated floating gate of polycrystalline silicon is formed on the sidewalls of the trench. Doped regions are formed on the surface of the substrate and in the trench bottom. A control gate is formed over the floating gate. Electrical contact is established to the doped regions and the control gate.

Inventors: Yang; Ming-Tzong (Hsinchu, TW)

Assignee: United Microelectronics Corporation (Hsinchu, TW)

Application Number: 07/977,186

Issued: 1993-11-02

Expired: 2005-11-02

Classes: 257/316 ; 257/331; 257/E21.209; 257/E21.422; 257/E21.693; 365/185.18

Field of search: 257/316,330,331,334 365/185

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