Method of forming semiconductor device including a CMOS structure having double-doped channel regions

U.S. Patent Number: 5290714

Abstract: A semiconductor device has, in one embodiment, a p type insulated gate field effect transistor formed in an n type well formed on a semiconductor substrate and an n type insulated gate field effect transistor formed in a p type well formed on the semiconductor substrate. Each of the p type and n type insulated gate-field effect transistors has a composite impurity layer under its gate electrode in a surface portion of its associated well. The composite impurity layer includes a first doped layer of a p type and a second doped layer of an n type adjacent thereto to form a pn junction layer therebetween, while the composite impurity layer includes a first doped layer of a p type and a second doped layer of a p type adjacent thereto to form a junction layer therebetween having a p type impurity concentration lower than that of the p type well.

Inventors: Onozawa; Kazunori (Takasaki, JP)

Assignee: Hitachi, Ltd. (Tokyo, JP)

Application Number: 07/941,825

Issued: 1994-03-01

Expired: 2006-03-01

Classes: 438/207 ; 148/DIG.9; 257/E21.633; 257/E21.696; 257/E27.015; 257/E27.067; 438/208; 438/217

Field of search: 437/27,45,59,34,29,57 148/DIG.9,DIG.82

Click the image above to view patent images at uspto.gov within a frame.

Click here for the fulltext page on uspto.gov within a frame.