Stacked chip assembly and manufacturing method therefor

U.S. Patent Number: 5311401

Abstract: Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed-wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.

Inventors: Gates, Jr.; Louis E. (Westlake Village, CA); Cochran; Richard K. (Ingelwood, CA)

Assignee: Hughes Aircraft Company (Los Angeles, CA)

Application Number: 07/727,500

Issued: 1994-05-10

Expired: 2006-05-10

Classes: 361/760 ; 174/255; 257/686; 257/E21.705; 257/E25.013; 361/744; 361/748; 361/772; 361/777; 361/813

Field of search: 361/396,397,400,401,404,421,735,744,748,760,761,772,775,777,807,813,792 357/65,70,71 174/255,260 257/686,690,700,786

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