Non-volatile semiconductor memory device having thin film memory transistors stacked over associated selecting transistors

U.S. Patent Number: 5321286

Abstract: A electrically erasable and programmable read only memory device has a memory cell array implemented by a plurality of floating gate type memory transistors, and each of the floating gate type memory transistors is implemented by a thin film field effect transistor with a floating gate electrode formed on a relatively thick insulating film covering a major surface of a semiconductor substrate so that the biasing conditions and crystal defects do not have any influence on the floating gate type memory transistor.

Inventors: Koyama; Shoji (Tokyo, JP), Inoue; Tatsuro (Tokyo, JP)

Assignee: NEC Corporation (JP)

Application Number: 07/978,899

Issued: 1994-06-14

Expired: 2006-06-14

Classes: 257/315 ; 257/314; 257/349; 257/57; 257/67; 257/71; 257/E27.026; 257/E27.103; 365/185.13

Field of search: 257/315,349,66,67,71,57,314 365/185

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