Method for optimally placing components of a VLSI circuit

U.S. Patent Number: 5349536

Abstract: In a method for placement of components for a VLSI circuit, an initial number of current placements are selected. A greedy optimization is partially performed on each of the current placements. Then, a subset of the current placements which have been partially optimized is selected to be the new current placements. This selection is based on a global cost metric for the current placements. The global cost metric is, for example, based on the total length of all connection line networks for the circuit. The partial optimization and selection are repeated until there is only one current placement. Then, an optimization is performed on the remaining placement to obtain an optimized placement. The optimization is, for example, a completion of the partially performed greedy optimization.

Inventors: Ashtaputre; Sunil V. (San Jose, CA), Wong; Dale M. (San Francisco, CA)

Assignee: VLSI Technology, Inc. (San Jose, CA)

Application Number: 07/747,542

Issued: 1994-09-20

Expired: 2006-09-20

Classes: 716/9

Field of search: 364/488,489,490,491

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