Method for sizing widths of power busses in integrated circuits

U.S. Patent Number: 5349542

Abstract: Segments within a power network of an integrated circuit are calculated utilizing information generated during design and placement. The performance of logic blocks within the integrated circuit is simulated to obtain an estimated maximum current requirement for each logic block. After obtaining an estimated maximum current requirement for each logic block, the estimated maximum current flow through each power net segment is obtained by summing the estimated current requirements for each logic block which draws current through the power net segment. Based on this estimated maximum current flow through each power segment, a width for each power net segment is calculated. After widths have been calculated, a check may be made to assure that a predetermined electromigration limit is not exceeded. When projected current flow through a power net segment will result in an exceeding of the predetermined electromigration limit, the width of the power net segment is increased.

Inventors: Brasen; Daniel R. (San Jose, CA), Seiler; Bruce S. (Fremont, CA)

Assignee: VLSI Technology, Inc. (San Jose, CA)

Application Number: 07/862,095

Issued: 1994-09-20

Expired: 2006-09-20

Classes: 703/15 ; 257/E23.151; 703/13; 716/13

Field of search: 364/488,489,490,491,578

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