Memory compiler with multiple selectable core elements

U.S. Patent Number: 5349552

Abstract: Methods and devices for efficiently using substrate space to form memory devices on integrated circuits, and in particular, in application specific integrated circuits. More particularly, a shared decoder and control logic are used for selectively accessing and addressing plural types of memory (e.g., RAM and ROM cells). Further, each memory cell of a memory array is programmed as a particular type of memory cell during circuit layout design. Therefore, specific rows, columns, or single bits of the memory cell array can be designated as specific types of memory.

Inventors: Zampaglione; Michael A. (San Jose, CA)

Assignee: VLSI Technology, Inc. (San Jose, CA)

Application Number: 07/811,401

Issued: 1994-09-20

Expired: 2006-09-20

Classes: 365/51 ; 365/63

Field of search: 365/51,63

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