Method of cancelling offset errors in phase detectors

U.S. Patent Number: 5351000

Abstract: A phase detector circuit which includes a first fixed delay circuit responsive to the first input signal for producing a fixedly delayed first signal which is a replica of a first input signal and delayed relative thereto by a fixed delay, a second fixed delay circuit responsive to a second input signal for producing a fixedly delayed second signal which is a replica of the second input signal and delayed relative thereto by the fixed delay, a controlled delay circuit responsive to the second input signal for producing a controllably delayed second signal and delayed relative thereto by a controlled delay, a first phase detector responsive to the fixedly delayed first signal and the adjustably delayed second signal for providing a first phase detector output that comprises the output of the phase detector circuit, a second phase detector circuit responsive to the fixedly delayed second signal and the adjustably delayed second signal for providing a second phase detector output, and an integrator responsive to the addition circuit output for controlling the controlled delay circuit to set the controlled delay such that the second phase detector output indicates zero phase error, whereby the controlled delay compensates the offset error of the first phase detector.

Inventors: Farwell; William D. (Thousand Oaks, CA)

Assignee: Hughes Aircraft Company (Los Angeles, CA)

Application Number: 08/099,886

Issued: 1994-09-27

Expired: 2006-09-27

Classes: 324/76.77 ; 324/601; 324/76.79; 327/3; 327/307

Field of search: 324/76.79,76.77,601 328/155,133,63,55

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