Technique and apparatus for testing an electrically programmable ROM embedded among other digital circuitry on an IC chip

U.S. Patent Number: 5371748

Abstract: A method and apparatus for testing an electrically programmable read-only-memory which is embedded within logic or other digital circuitry on an integrated circuit is described. An integrated circuit tester is used to test the electrically programmable read-only-memory along with the logic or other digital circuitry by encoding certain test channels of the integrated circuit tester, and inputting the encoded test channels into a high voltage signal decoding circuit specially adapted to generating a high voltage, programming voltage required by the electrically programmable read-only-memory when the programming of certain test bits in the electrically programmable read-only-memory is conducted.

Inventors: Saw; Beng I. (San Jose, CA), Tai; Marcus V. (San Jose, CA), Le; Dai M. (San Jose, CA)

Assignee: VLSI Technology, Inc. (San Jose, CA)

Application Number: 08/037,957

Issued: 1994-12-06

Expired: 2006-12-06

Classes: 714/740 ; 702/119; 714/718; 714/719; 714/734

Field of search: 324/73.1 364/579,580 371/21.1,21.2,22.6,24,27

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