Method for testing a semiconductor device on a universal test circuit substrate

U.S. Patent Number: 5378981

Abstract: A low cost method is used to standardize testing of bare semiconductor devices. In one embodiment, a universal test circuit substrate (10) having an interleaving fan-out pattern of conductive traces (14) is provided. The radial array of conductive traces terminates in a plurality of test pads (16) placed in a standard pattern around a periphery of a central die accommodating region. A die cavity (36), slightly larger than the size of a semiconductor die (32) to be tested, is formed in the central die accommodating region. The semiconductor die is placed approximately centered in the die cavity and is wire bonded (40) to individual traces of the pattern of conductive traces. The die can be tested and burned-in on the universal test circuit substrate with a test probe making contact with the test pads. The universal test circuit substrate can accommodate a multiplicity of die sizes and pin-out requirements of semiconductor devices.

Inventors: Higgins, III; Leo M. (Austin, TX)

Assignee: Motorola, Inc. (Schaumburg, IL)

Application Number: 08/012,193

Issued: 1995-01-03

Expired: 2007-01-03

Classes: 324/765 ; 257/E23.055; 257/E23.065; 324/158.1; 361/772

Field of search: 324/158R,158F 437/8 257/668,670,689 361/772,774

Click the image above to view patent images at uspto.gov within a frame.

Click here for the fulltext page on uspto.gov within a frame.