Design for encapsulation of thermally enhanced integrated circuits

U.S. Patent Number: 5379187

Abstract: An improved packaging technique for packaging a thermally-enhanced, molded-plastic quad flat package (TE-QFP). An integrated-circuit die is attached to a thermally conductive, electrically-insulated substrate having a stepped area formed into the outer margins thereof. A lead frame has inwardly-extending fingers, which are attached to the stepped areas in the outer margins of the thermally conductive, electrically-insulated substrate. The stepped area centers the thermally conductive, electrically-insulated substrate and attached integrated-circuit die within the mold cavity so that the flow of plastic material is balanced over the top and bottom of the substrate to provide a molded package body substantially free of voids.

Inventors: Lee; Sang S. (Sunnyvale, CA), Fujimoto; George (Santa Clara, CA)

Assignee: VLSI Technology, Inc. (San Jose, CA)

Application Number: 08/037,059

Issued: 1995-01-03

Expired: 2007-01-03

Classes: 361/707 ; 174/529; 174/536; 257/720; 257/787; 257/E21.504; 257/E23.036; 257/E23.038; 257/E23.092; 361/713; 361/813

Field of search: 165/80.3,185 174/52.2,52.4 257/705-707,711,713,720,725,753,787,792,796 264/272.11 361/761,764,774,776,792,704,707,713,723,783,790,794,795,813,749 437/210,211,220

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