Method for manufacturing anti-fuse structures

U.S. Patent Number: 5387311

Abstract: A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.

Inventors: Hall; Stacy W. (San Antonio, TX), Delgado; Miguel A. (San Antonio, TX)

Assignee: VLSI Technology, Inc. (San Jose, CA)

Application Number: 08/017,542

Issued: 1995-02-07

Expired: 2007-02-07

Classes: 438/600 ; 148/DIG.55; 257/E21.592; 257/E23.147

Field of search: 156/630,633 437/922,44 148/DIG.55 257/529,530

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