Switch array power reduction apparatus

U.S. Patent Number: 5390333

Abstract: In a multinode switch array, the maximum number of nodes that can be passing data from input to output lead can be no greater than the number of output leads in the array. Thus, the remaining nodes, while not performing a useful switch function, when implemented in CMOS (complementary metal oxide semiconductor), are consuming power due to changing logic levels in the circuitry and are causing the input data drivers to consume power due to the loading effect of the non-functional but actively connected nodes. The present invention overcomes these prior art disadvantages by ascertaining from the indirect address data stored in connect memory of each node, the times that the traffic memory needs to be activated and deactivates the memory and any associated driver at all other times in a manner such that it and the data driver are not consuming power incurred by data transfer operations.

Inventors: Pritt; Harley P. (Rockwall, TX), Zeeff; Michael A. (Richardson, TX), Littlewood; Paul A. (Plano, TX)

Assignee: Alcatel Network Systems, Inc. (Richardson, TX)

Application Number: 07/963,507

Issued: 1995-02-14

Expired: 2007-02-14

Classes: 713/324 ; 365/227; 711/211

Field of search: 395/750,425,725,325,550,400 365/189.04,227 370/68,58.1,111 364/273.1,273.5,DIG.1,942,948.8,948.91,DIG.2,707

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