Integrated logic circuit

U.S. Patent Number: 5391905

Abstract: A logic circuit comprising an active-pull-down circuit in which electrodes of an active capacitor are formed of a conductive layer in common with one of contact electrodes of neighboring transistors is disclosed. The area for the capacitor is reduced, so that the element-occupied area is minimum even when the absorbing capability of the active-pull-down circuit is designed to be high for reducing a transient duration of an output signal. Besides, capacitor insulation film is used as a mask during a process, so that the process for fabrication of the integrated circuit is simplified.

Inventors: Yamazaki; Tohru (Tokyo, JP)

Assignee: NEC Corporation (Tokyo, JP)

Application Number: 07/926,000

Issued: 1995-02-21

Expired: 2007-02-21

Classes: 257/370 ; 257/344; 257/346; 257/378; 257/577; 257/588; 257/607; 257/E27.015; 257/E27.02

Field of search: 257/370,378,577,587,588

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