Semiconductor device having multi-level wiring

U.S. Patent Number: 5391921

Abstract: A semiconductor device that has a feature in the spatial relationship between the wiring in a multi-level wiring and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wiring there exist intermediate insulating films that have a pattern which is the same as the pattern of the wiring. Because of this arrangement, the intermediate insulating film does not exist between the wiring on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure. As a result of realization of such structures, in the semiconductor device according to the present invention, the parasitic capacitance due to the coupling capacitances between the wiring can be reduced compared with a semiconductor device that has a structure in which the spaces between the wiring are filled with the intermediate films.

Inventors: Kudoh; Osamu (Tokyo, JP), Okada; Kenji (Tokyo, JP), Shiba; Hiroshi (Tokyo, JP), Katoh; Takuya (Tokyo, JP)

Assignee: NEC Corporation (Tokyo, JP)

Application Number: 08/083,322

Issued: 1995-02-21

Expired: 2007-02-21

Classes: 257/758 ; 257/734; 257/759; 257/760; 257/765; 257/773; 257/774; 257/776; 257/E21.576; 257/E21.581; 257/E23.144; 257/E23.167

Field of search: 357/68,71,74,65 257/734,758,759,760,765,773,774,776

Click the image above to view patent images at uspto.gov within a frame.

Click here for the fulltext page on uspto.gov within a frame.