Testing circuit provided in digital logic circuits

U.S. Patent Number: 5392296

Abstract: A testing circuit for scan-pass testing an integrated circuit comprises a chain of serially connected scan-pass registers where an individual scan-pass register in the chain can be programmably selected for observation at a shift-out port located at the last scan-pass register in the serial chain. To programmably select a particular register, while a test signal is held active, a clock is pulsed and each clock pulse selects the next scan-pass register in the chain for observation, starting with the first scan-pass register. The register selected when the test signal becomes inactive is the register that is observed at the shift-out port at the end of the scan-pass register chain. The testing circuit permits the value of any register in the chain to be output in real-time without circuit interruption.

Inventors: Suzuki; Hiroaki (Tokyo, JP)

Assignee: NEC Corporation (JP)

Application Number: 07/937,653

Issued: 1995-02-21

Expired: 2007-02-21

Classes: 714/731 ; 714/724; 714/733

Field of search: 371/22.1,22.2,22.3,22.4,22.5,22.6 324/73.1,158R

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