|
Pattern recognition apparatus
U.S. Patent Number: 5392366
Abstract: In a pattern recognition apparatus constituted by a one-chip LSI (large scale integrated), product-sum calculations are performed between an input pattern to be recognized and a plurality of reference patterns by a product-sum circuit. The plurality of reference patterns are stored in an external memory used as a dictionary. The similarity values obtained by the product-sum calculations are subjected to floating processing in a floating circuit. The similarity values, which have undergone floating processing, are sorted in the order of larger magnitudes. The sorted similarity values are read out by a host CPU (central processing unit).
Inventors: Nakamura; Yoshikatu (Yokosuka, JP)
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Application Number: 07/841,326
Issued: 1995-02-21
Expired: 2007-02-21
Classes: 382/209 ; 382/218
Field of search: 382/30,34,33,41,49,39
|
Click the image above to view patent images at uspto.gov within a frame.
Click here for the fulltext page on uspto.gov within a frame.
|