Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation

U.S. Patent Number: 5392416

Abstract: A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

Inventors: Doi; Toshio (Kokubunji, JP), Takemoto; Takeshi (Sagamihara, JP), Nakatsuka; Yasuhiro (Palo Alto, CA)

Assignee: Hitachi, Ltd. (Tokyo, JP)

Application Number: 08/103,791

Issued: 1995-02-21

Expired: 2007-02-21

Classes: 711/3 ; 711/122

Field of search: 395/425,400 364/2MSFile,9MSFile

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