Method for forming a compact transistor structure

U.S. Patent Number: 5393681

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Inventors: Witek; Keith E. (Austin, TX), Fitch; Jon T. (Austin, TX), Mazure; Carlos A. (Austin, TX)

Assignee: Motorola, Inc. (Schaumburg, IL)

Application Number: 08/215,888

Issued: 1995-02-28

Expired: 2007-02-28

Classes: 438/301 ; 257/E21.41; 257/E27.026; 257/E27.108; 257/E29.116; 257/E29.121; 257/E29.122; 257/E29.187; 257/E29.262; 438/164; 438/300; 438/305

Field of search: 437/40,90,91,915,162,193,89

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