Method of manufacturing a stacked capacitor DRAM

U.S. Patent Number: 5393688

Abstract: A storage node of a stacked capacitor in a DRAM comprises a first part connected to a source/drain region and a second part protruding upward from a substrate in a vertical wall shape. The second part includes a concave part in the inner part which is removed by etching. Steps are formed on the inner and outer peripheral surfaces of the vertical wall part. The steps are formed by a self-alignment method using a sidewall insulating layer formed by anisotropic etching. Capacitance of the capacitor is increased by forming steps on the surface of the storage node.

Inventors: Motonami; Kaoru (Hyogo, JP), Okumura; Yoshinori (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)

Application Number: 08/156,749

Issued: 1995-02-28

Expired: 2007-02-28

Classes: 438/396 ; 257/E27.089; 438/701; 438/702

Field of search: 437/48,52,60,919

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