Process for manufacturing semiconductor components

U.S. Patent Number: 5393711

Abstract: A process for manufacturing semiconductor components, especially diodes. The process entails first bonding two semiconductor wafers of different conducting types (p and n), according to a silicon-fusion bonding process (SFB), thereby forming a bonded wafer assembly with a p-n junction. The bonded wafers are then partitioned into a plurality of semiconductor elements by the cutting of grooves into the bonded wafers to a depth which extends at least to the p-n junction. Each of the plurality of semiconductor elements thus formed has an individual p-n junction with sides exposed by the grooves. The sides of the semiconductor elements are then subjected to etching and passivation. The upper and lower surfaces of the bonded wafer assembly are then metal-coated. Finally, the semiconductor elements are separated from each other by a sawing operation.

Inventors: Biallas; Vesna (Ruetlingen, DE), Goebel; Herbert (Ruetlingen, DE), Spitz; Richard (Ruetlingen, DE)

Assignee: Robert Bosch GmbH (Stuttgart, DE)

Application Number: 08/211,670

Issued: 1995-02-28

Expired: 2007-02-28

Classes: 438/458 ; 148/DIG.135; 257/E21.088; 257/E21.228; 257/E21.238; 257/E21.599; 438/462; 438/465

Field of search: 437/231,226,228,915,974 148/DIG.135

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