SRAM memory cell with tri-level local interconnect

U.S. Patent Number: 5394358

Abstract: A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor. In a complementary fashion, the "false" inter-level interconnect connects: the drain of the "false" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "true" pull-up transistor and the "true" pull-down transistor, and a diffusion region defining and connecting the drain of the "false" access transistor and the drain of the "false" pull-down transistor. These two five-way connections provide all the necessary local interconnections for the memory cell. The reduced number of inter-level local interconnects required provides for denser memory cell layouts.

Inventors: Huang; Tiao-Yuan (Cupertino, CA)

Assignee: VLSI Technology, Inc. (San Jose, CA)

Application Number: 08/219,693

Issued: 1995-02-28

Expired: 2007-02-28

Classes: 365/182 ; 257/401; 257/903; 257/E27.099; 365/180

Field of search: 365/180,182,154 257/327,369,371,383,393,401,903

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