Arrangement for predicting a branch target address in the second iteration of a short loop

U.S. Patent Number: 5394530

Abstract: Improved techniques for predicting a branch target address using a branch history table (BHT), is disclosed. The BHT stores a plurality of pairs of a branch address and corresponding branch target address. In order to eliminate or effectively reduce loss of machine cycles in the branch target address prediction, a prefetched address data is compared with an incoming new branch instruction address before being applied to a BHT (branch history table) for the purpose of updating same. When the coincidence is detected, a selector selects a new branch target address before being applied to the BHT. The selected new branch target address is fed to an instruction address prefetch register.

Inventors: Kitta; Mayumi (Yamanashi, JP)

Assignee: NEC Corporation (Tokyo, JP)

Application Number: 08/199,970

Issued: 1995-02-28

Expired: 2007-02-28

Classes: 712/240 ; 711/213

Field of search: 395/375

Click the image above to view patent images at uspto.gov within a frame.

Click here for the fulltext page on uspto.gov within a frame.