Fet device with double spacer

U.S. Patent Number: 5663586

Abstract: An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

Inventors: Lin; Jengping (Taiwan, CN)

Assignee: United Microelectronics Corporation (Hsin-chu, TW)

Application Number: 08/592,154

Issued: 1997-09-02

Expired: 2005-09-02

Classes: 257/336 ; 257/340; 257/344; 257/900; 257/E21.626; 257/E29.141; 257/E29.15; 257/E29.269

Field of search: 257/336,340,344

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