Method for fabricating trench/stacked capacitors on DRAM cells with increased capacitance

U.S. Patent Number: 5665624

Abstract: A method is described for making an array of dynamic random access memory (DRAM) cells having a trench/stacked capacitor within each cell. The method involves forming trenches in the silicon substrate at the capacitor node contact areas of the DRAM cells, and using liquid phase deposition (LPD) of silicon oxide in the trenches to form oxide plugs that extend upward into the openings in the photoresist mask used to etch the trenches. After removing the photoresist, polysilicon sidewall spacers are formed on the LPD oxide plugs. The sidewall spacers become part of the stacked capacitor structures. Another patterned polysilicon layer is used to form the array of storage-node electrodes for the stacked capacitors, and also serve as the storage-node electrodes for the trench capacitors. Conventional methods are used to complete the array of trench/stacked capacitors by depositing an interelectrode dielectric layer and then forming the polysilicon top electrodes.

Inventors: Hong; Gary (Hsin-Chu, TW)

Assignee: United Microelectronics Corporation (Hsin-Chu, TW)

Application Number: 08/735,221

Issued: 1997-09-09

Expired: 2005-09-09

Classes: 438/244 ; 257/E27.094; 438/249; 438/387

Field of search: 437/47,52,60,919,203

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