Field effect transistor with recessed buried source and drain regions

U.S. Patent Number: 5705840

Abstract: The invention describes recessed source/drain regions formed in trenches in the substrate that provide a smooth surface topology, smaller devils and improved device performance. The recessed source/drain regions have two conductive regions: the first upper lightly doped region on the trench sidewalls, and the second lower region under the trench bottom. In addition, two buried layers are formed between adjacent source/drain regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the lower source/drain regions on the trench bottoms. The upper lightly doped source/drain region and the anti-punchthrough layer have the effect of increasing the punchthrough voltage without increasing the threshold voltage. The upper and lower source/drain regions lower the overall resistivity of the source/drain allowing use of smaller line pitches and therefore smaller devils. Overall, the recessed source/drain regions and the two buried layers allow the formation of smaller devices with improved performance.

Inventors: Shen; Shing-Ren (Tao-Yuan, TW), Su; Kuan-Cheng (Taipei, TW), Chung; Chen-Hui (Hsin-Chu, TW)

Assignee: United Microelectronics Corporation (Hsin-Chu, TW)

Application Number: 08/636,785

Issued: 1998-01-06

Expired: 2006-01-06

Classes: 257/344 ; 257/408; 257/E21.431; 257/E29.04; 257/E29.063

Field of search: 257/330,331,333,336,344,408 29/578 437/2,35

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