High density flash EPROM

U.S. Patent Number: 5721442

Abstract: A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.

Inventors: Hong; Gary (Hsin-Chu, TW)

Assignee: United Microelectronics Corporation (Hsin-Chu, TW)

Application Number: 08/847,876

Issued: 1998-02-24

Expired: 2006-02-24

Classes: 257/316 ; 257/330; 257/E21.422; 257/E21.693

Field of search: 257/316,315,329,330

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