Process of making a storage capacitor for dram memory cell

U.S. Patent Number: 5744388

Abstract: A storage capacitor structural configuration for memory cell units of DRAM devices and a process for constructing the capacitor. The capacitor includes a first electrode and a second electrode that are each electrically conducting layers, and a storage dielectric that is a dielectric layer sandwiched between the two electrodes. The silicon substrate of the device has formed thereon a field oxide layer and a transistor including a gate and a pair of source/drain regions. A first dielectric layer covers the transistor and includes a contact opening over one of the source/drain regions. The first electrode includes a first electrically conducting layer formed inside the contact opening and covering the revealed surface of the source/drain region and the first dielectric layer. A second electrically conducting layer having a rugged surface is formed on the surface of the first electrically conducting layer. A number of deep grooves are formed in the second and first electrically conducting layers, forming a grid-like configuration. The storage dielectric includes a second dielectric layer covering the surface of the grid-like configuration of the second and first electrically conducting layers. The second electrode includes a third electrically conducting layer that covers the surface of the storage dielectric.

Inventors: Chen; Anchor (Pingtung City, TW)

Assignee: United Microelectronics Corporation (TW)

Application Number: 08/661,384

Issued: 1998-04-28

Expired: 2006-04-28

Classes: 438/253 ; 257/E21.02; 438/254

Field of search: 361/311-313,320,321.1,321.2,321.3,321.4,321.5 438/393-399,239,250-256 29/25.42 427/79

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