Input detector

U.S. Patent Number: 5818267

Abstract: In respective comparators, a plurality of input voltages are compared with a comparison voltage that has been swept, and only the binary output of a D flipflop corresponding to the comparator that has exceeded the comparison voltage earliest is allowed to have "1", while the outputs corresponding to the rest of the comparators have "0". Therefore, it is possible to detect a maximum output by using the comparators of a normal CMOS construction and a binary-change detection means circuit constituted by logical circuits. Compared with the application of floating-gate MOS, this arrangement makes it possible to reduce costs, and also to easily carry out offset-voltage compensation for each comparator by using switched capacitors. As a result, in a maximum input detector which detects a maximum input from analog inputs through multiple channels by carrying out analog operations, it is possible to reduce costs, and also to improve detection precision.

Inventors: Fujio; Mitsuhiko (Iizuka, JP), Miyamoto; Masayuki (Nabari, JP), Iizuka; Kunihiko (Sakai, JP), Matsui; Hirofumi (Ikoma-gun, JP)

Assignee: Sharp Kabushiki Kaisha (Osaka, JP)

Application Number: 08/808,565

Issued: 1998-10-06

Expired: 2006-10-06

Classes: 327/58 ; 327/307

Field of search: 327/58-62,70,91,94-96,307,337,554

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