Method of fabricating a semiconductive device

U.S. Patent Number: 6291354

Abstract: A method of fabricating a semiconductor device is described in which an insulation layer is formed over the gate electrode and the substrate. This insulation layer is anisotropically etched away except for a portion surrounding the sidewall of the gate electrode to form a spacer. The tip of the spacer is at the same height as the upper surface of the liner layer and is lower than the upper surface of the gate electrode, therefore, resulting in an increase of the exposed area of the gate electrode surface.

Inventors: Hsiao; Hsi-Mao (Hsinchu, TW), Chen; Chun-Lung (Tainan Hsien, TW), Yu; H. C. (Yi-Lan Hsien, TW), Lin; Hsi-Chin (Hsinchu Hsien, TW)

Assignee: United Microelectronics Corp. (Hsinchu, TW)

Application Number: 09/315,799

Issued: 2001-09-18

Expired: 2005-09-18

Classes: 438/701 ; 257/E21.252; 257/E21.438; 257/E21.439; 438/305; 438/592; 438/595; 438/655; 438/682; 438/696; 438/714; 438/734; 438/740

Field of search: 438/305,592,595,655,682,701,696,734,714,723,724,740

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