MOSFET test structure for capacitance-voltage measurements

U.S. Patent Number: 6472233

Abstract: An apparatus and method used in extracting polysilicon gate doping from C-V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 .mu.m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

Inventors: Ahmed; Khaled Z. (Newport Beach, CA), Bui; Nguyen D. (San Jose, CA), Ibok; Effiong (Sunnyvale, CA), Hauser; John R. (Raleigh, NC)

Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)

Application Number: 09/586,960

Issued: 2002-10-29

Expired: 2006-10-29

Classes: 438/14 ; 257/288; 324/500; 324/769; 438/18; 438/197

Field of search: 438/14,18,197 257/288 324/769,500

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