TFT panel alignment and attachment method and apparatus

U.S. Patent Number: 6487461

Abstract: A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.

Inventors: Gaynes; Michael A. (Vestal, NY), Johnson; Allan O. (Johnson City, NY), Kodnani; Ramesh R. (Binghamton, NY), Pierson; Mark V. (Binghamton, NY), Tasillo; Edward J. (Newark Valley, NY)

Assignee: International Business Machines Corporation (Armonk, NY)

Application Number: 09/590,280

Issued: 2002-11-26

Expired: 2006-11-26

Classes: 700/58 ; 156/104; 156/106; 156/286; 156/87; 345/589; 345/88; 345/903; 349/153; 349/187; 349/190; 349/73; 455/24; 455/60; 700/54; 700/56; 700/57; 700/62; 700/64

Field of search: 700/56,57,58,59,60,61,62,64 445/24,60 349/187,73-75,153,158,156,149,190,78 345/88,903,1.3,589 156/104,106,286,87,300

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