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Expired patents of:
VLSI Technology, Inc.

Displaying 101 to 150 of 266 patents. (Retrieval took 2.050 seconds.)

 Patent TitleExpired:
101.Thermal trap for gaseous materials2006-04-19
102.System for protecting leads of a semiconductor chip package during testing, burn-in and handling2006-04-19
103.Use of optimized film stacks for increasing absorption for laser repair of fuse links2006-04-16
104.Digital counter test circuit2006-04-14
105.System for passing Industry Standard Architecture (ISA) legacy interrupts across Peripheral Component Interconnect (PCI) connectors and methods therefor2006-04-14
106.Technique for measuring thermal resistance of semiconductor packages and materials2006-04-12
107.Programmable boundary between system board memory and slot bus memory2006-04-12
108.Link system controller interface linking a PCI bus to multiple other buses2006-04-07
109.Computer bus mastery system and method having a lock mechanism2006-04-07
110.Reliability qualification vehicle for application specific integrated circuits2006-03-29
111.Apparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI bus2006-03-24
112.Tab magazine loader and method using a slider mechanism2006-03-22
113.Lead frame assembly and method for wiring same2006-03-22
114.Box for an optical stepper reticle2006-03-22
115.Finite impulse response filter2006-03-22
116.Semiconductor wafer manufacturing process with high-flow-rate low-pressure purge cycles2006-03-17
117.Method for predicting capacitance of connection nets on an integrated circuit2006-03-15
118.Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication2006-03-10
119.Digital-to-analog converter and bias compensator therefor2006-03-08
120.VCO circuit using negative feedback to reduce phase noise2006-03-05
121.Method of manufacturing amorphous silicon antifuse structures2006-03-03
122.Automatic cache controller system and method therefor2006-03-03
123.Method for making anti-fuse structures2006-03-01
124.BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure2006-02-22
125.Integrated-circuit processing with progressive intermetal-dielectric deposition2006-02-15
126.Illegal address detector for semiconductor memories2006-02-15
127.Method for providing an improved fully associative cache memory having a finite state machine and linked list structure2006-02-10
128.Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric2006-02-08
129.Asymmetric drain/source layout for robust electrostatic discharge protection2006-02-03
130.Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value2006-01-18
131.Variable sized FIFO memory and programmable trigger level therefor for use in a UART or the like2006-01-11
132.Von Neumann system with harvard processor and instruction buffer2006-01-06
133.Autocalibrating trip controller with dual adjustable trip points2006-01-04
134.Integrated-circuit via formation using gradient photolithography2005-12-30
135.Sloped silicon nitride etch for smoother field oxide edge2005-12-30
136.Method of reducing contact resistance for semiconductor manufacturing processes using tungsten plugs2005-12-23
137.Design for sputter targets to reduce defects in refractory metal films2005-12-21
138.Computer system permitting mulitple write buffer read-arounds and method therefor2005-12-09
139.Methods and apparatus for calculating alignment of layers during semiconductor processing2005-12-04
140.Timing system for mobile cellular radio receivers2005-12-02
141.Method for forming channel-region doping profile for semiconductor device2005-11-27
142.Temperature, process and voltage variant slew rate based power usage simulation and method2005-11-25
143.Method of assembling and cooling a package structure with accessible chip2005-11-18
144.Universal contactor system for testing ball grid array (BGA) devices on multiple handlers and method therefor2005-11-18
145.Multi-layer substrate structure2005-11-18
146.Method and apparatus for compacting integrated circuits with wire length minimization2005-11-18
147.Tungsten plugs for integrated circuits and method for making same2005-11-13
148.Adjustable fixture for use with a wire pull tester2005-11-11
149.Apparatus for bonding a semiconductor die to a package using a gold/silicon preform and cooling the die and package through a monotonically decreasing temperature sequence2005-11-09
150.Method for bonding a lead to a die pad using an electroless plating solution2005-11-09

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